`timescale 1ns / 1ps

module prbs_top (
    input  wire        clk,
    input  wire        rst_n,
    input  wire        test_enable,
    input  wire [7:0]  test_seed,
    output wire        prbs_signal,
    output wire        sync_detected,
    output wire        error_flag,
    output wire [15:0] bit_errors,
    output wire [7:0]  gen_state,
    output wire [7:0]  det_state
);

    // 内部信号
    wire prbs_data;
    
    // PRBS生成器实例
    prbs_generator u_generator (
        .clk        (clk),
        .rst_n      (rst_n),
        .enable     (test_enable),
        .seed       (test_seed),
        .prbs_out   (prbs_data),
        .lfsr_state (gen_state)
    );
    
    // PRBS检测器实例
    prbs_detector u_detector (
        .clk            (clk),
        .rst_n          (rst_n),
        .enable         (test_enable),
        .prbs_in        (prbs_data),
        .expected_seed  (test_seed),
        .sync_found     (sync_detected),
        .error_detected (error_flag),
        .error_count    (bit_errors),
        .detector_state (det_state)
    );
    
    // 输出连接
    assign prbs_signal = prbs_data;
    
endmodule